The architecture of a field programmable gate array (FPGA) typically includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). The IOBs provide the interface between the package pins and the CLBs, whereas the CLBs provide the functional elements for constructing logic on the FPGA. The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. The CLBs, IOBs, and programmable routing resources contain configuration memories that must be configured before each CLB, IOB, or routing resource can perform a specified function.
Typically, the configuration memories within an FPGA use static random access memory (SRAM) cells that are programmed by loading a configuration bitstream into the FPGA. Specific examples for configuring various FPGAs can be found on pages 6-60 to 6-68 of “The Programmable Logic Data Book 1999” (hereinafter “The Xilinx 1999 Data Book”), published in March, 1999 by Xilinx, Inc., and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. Additional methods to program FPGAs are described by Lawman in U.S. Pat. No. 6,028,445, entitled “DECODER STRUCTURE AND METHOD FOR FPGA CONFIGURATION” by Gary R. Lawman, filed Dec. 30, 1997 and issued Feb. 22, 2000. U.S. Pat. No. 6,366,117 entitled “NONVOLATILE/BATTERY-BACKED KEY IN PLD” by Pang et al., filed Nov. 28, 2000 and issued Apr. 2, 2002, describes structures and methods for using encrypted bitstreams in FPGAs. These patents are also incorporated herein by reference.
A configuration bitstream provides a portable, convenient means for a vendor to distribute configuration information (sometimes referred to as intellectual property, or IP) for proprietary system designs to users. The user benefits from this IP because the user does not need to spend the time or resources to develop the logic implemented by the bitstream, while the vendor profits from being able to sell the same IP to multiple users. However, this very same ease of distribution also makes bitstream IP highly susceptible to unauthorized use, since stolen or otherwise unauthorized copies of configuration bitstream data can be used to configure any number of FPGA systems. Therefore, configuration bitstreams are typically encrypted to prevent this type of misappropriation.
FIG. 1a shows a conventional FPGA 100a that includes bitstream decryption circuitry. FPGA 100a includes a secure key register 110a powered by a battery backup 111, a bitstream decoder circuit 130, programming circuitry 140, and reprogrammable logic 150 (which includes configuration memory, CLBs, IOBs, and programmable routing resources). An encrypted configuration bitstream BSe is provided to bitstream decoder circuit 130, which also receives a decryption key KEY from secure key register 110a. Using decryption key KEY, bitstream decoder circuit 130 decrypts encrypted bitstream BSe and provides a decrypted bitstream BSd to programming circuitry 140. Programming circuitry 140 then loads decrypted bitstream BSd into reprogrammable logic 150 to configure FPGA 100a. 
FIG. 1b shows another conventional FPGA 100b that includes bitstream decryption circuitry, but avoids the requirement of a battery backup by incorporating a permanent decryption key storage structure. Like FPGA 10a shown in FIG. 1a, FPGA 100b includes a bitstream decoder circuit 130 for decrypting an encrypted bitstream BSe and programming circuitry 140 that loads decrypted bitstream BSd from bitstream decoder circuit 130 into reprogrammable logic 150 through programming circuitry 140. However, rather than using a battery-backed register to store and provide decryption key KEY to bitstream decoder circuit 130, FPGA 100b includes an embedded key structure 110b that is, for example, formed during device fabrication using custom masks, or during a post-fabrication modification process using a localized technique such as laser etching, antifuse programming, or programming of a non-volatile memory.
By using encrypted bitstream BSe, both FPGAs 100a and 100b make the copying of customer IP much more difficult, since the encrypted bitstream cannot be used without decryption key KEY. However, this enhanced bitstream protection increases design and production costs, as the vendor must implement either a battery backup system or else must incorporate custom processing steps to create an embedded key structure. Furthermore, if an unauthorized copyist obtains decryption key KEY, the protection of the bitstream IP is completely lost. FPGAs 100a and 100b attempt to maintain decryption key security by storing decryption key KEY within internal registers (i.e., secure register 110a and embedded key structure 110b, respectively), so that decryption key KEY cannot simply be read off of any of the FPGA I/O pins. However, a dedicated copyist can still probe the internal (die) connections of secure key register 110a (shown in FIG. 1a) or embedded key structure 110b (shown in FIG. 1b) to extract decryption key KEY.
Accordingly, it is desirable to provide a system and method for protecting bitstream IP that minimizes the possibility of unauthorized configuration bitstream use.